module top_module (
    input clk,
    input a,
    output [3:0] q );

	always@(posedge clk)begin
		if(~a)begin
			if(q<4'h6)
				q<=q+4'h1;
			else
				q<=4'h0;
		end
		else
			q<=4'h4;
	end
	
endmodule